This invention relates to a signal processing apparatus for correcting a time base variation of a video signal output by an image producing apparatus.
In magnetic recording/reproducing apparatuses such as a VTR or image reproducing apparatuses such as a video disk apparatus, a time base variation in the reproduced video signal occurs due to a variation in the relative position between a signal detecting medium such as a magnetic head or a pickup head and a recording medium such as a magnetic tape or disk. When the time base variation is moderate, a gentle change of the time base will cause a jitter in the reproduced picture. On the other hand, when the time base is subjected to rapid changes, a vast change of the time base will cause a skew in the reproduced picture.
As described above, those reproducing apparatuses have a intrinsic drawback of notably impairing the stability of the reproduced images.
As a reproduced video signal processing apparatus to correct the time base variation, a video signal processing apparatus shown in FIG. 1 has been well-known and is described, for example, in Japan Broadcast Publishing Co., Ltd., Hoso Gijutsu Sohsho Vol. 5: VTR Technology, Chapter 6.
In FIG. 1, reference numeral 10 indicates an input terminal of a video signal having time base variations and 20 indicates an output terminal of the video signal in which the time base variations have been corrected. Reference numeral 1 indicates an A/D converter circuit to convert an input video signal into a digital signal, 2 a RAM (a memory which permits quick direct access to a memory location for reading or writing data at any time). Reference numeral 4 indicates a synchronizing separation circuit, which extracts horizontal synchronizing signals containing time base variations from the composite video signal. The horizontal synchronizing signals are supplied to a write clock generator circuit 40 and a write address control circuit 70.
Synchronized with the above-mentioned horizontal synchronizing signals, the write clock generator circuit 40 generates write clock pulses timed with the time base variations of the input video signal from terminal 10. The write address control circuit 70 outputs a write address in step with the above-mentioned write clock pulses. The video signal having the time base variations coming from the terminal 10 is converted into a digital signal successively by the A/D converter circuit 1 in step with the write clock pulses, and is written at specified addresses in the memory 2.
On the other hand, stable reference synchronizing signals without time base variations are applied to a terminal 30. A read clock generator circuit 90 generates read clock pulses synchronized with the reference synchronizing signals. A read address control circuit 80 outputs a read address in step with the read clock pulses mentioned above. Therefore, digital data of the video signal stored in the memory 2 is read sequentially from the specified read addresses mentioned above. The digital data which has been read is converted sequentially into an analog signal in step with the read clock pulses by a D/A conversion circuit 3. As a result, a stable video signal without time base variation is output from terminal 20.
As mentioned earlier, the memory 2 is generally formed by a RAM, and if the number of samples of the input video signal in one horizontal scanning period (hereafter referred to as 1 H) is denoted by n, a correction amount of the time base variation by .+-.kH and the number of bits of the A/D converter circuit 1 by m, then the memory 2 requires a capacity of at least n.times.(2.times.k).times.m bits, and it is necessary to control N.times.(2.times.k) addresses. The address control is done by a counter, for example, and the control method is so complicated that the circuit has to be large in size, which has been a problem.
Above all, in write address control, the write addresses are controlled by the write address control circuit 70 according to the vertical and horizontal synchronizing signals included in the input video signal and also in step with the write clock pulses mentioned above. However, it is necessary to make considerable contrivances in designing the circuit to make up for lost vertical and horizontal and synchronizing signals to carry on specified write address control to store digital data from the A/D converter circuit 1 in the specified address area of the memory 2 when any of the vertical and horizontal synchronizing signals is lost. The signal processing method is complicated so that the circuit size has to be large, which has been another problem.
There is still another problem that if the synchronizing information which has dropped out fails to be interpolated, the specified signal processing mentioned above will be disturbed substantially.